Chip Test Series CP, FT, WAT Differences

The main differences between CP and FT.

(1) CP generally looks at the package before the test wafer, and then looks at the package to the FT wafer, whereas a bumped wafer is a tin ball, not an FT that is probed.

(2) FT is after the package, also called "final test". It means that after testing this channel, it will be sold directly for application.

The main effects of CP and FT:

(1) The main purpose of CP is to separate the film,failure analysis which can reduce the cost of packaging and testing, and more directly understand the yield of the wafer.

(2) FT is to pick out the NG chips and test the package yield. Now for general wafer process, many companies have omitted CP, in order to reduce cost. cp tests each core of the whole wafer, while FT tests the packaged chips. cp passes will be unpacked. Then FT to make sure the package is also Passed.

Grade: Wafer Acceptance Testing, Wafer Level Die or Structural Testing

For specialized testing through the graphics (test key) of the test, through the electrical parameters to monitor the various steps of the process design can be normal and stable; CP is wafer level chip probing, is the entire wafer process,wafer test including backgrinding and backmetal (if need), for some of the enterprise basic functional devices Structure parameters of the test, such as vt (threshold control voltage), Rdson (on-resistance), BVdss (source-drain breakdown voltage), Igss (gate-source leakage current), Idss (leakage-source leakage current), etc., the general system test workstation voltage and power must not have a very high; FT is the final test of packaged chip level. FT is the packaged chip level Final Test, mainly students for us (CP passed) IC or Device chip technology application research test, some countries even standby time test;

Pass FP is not enough, we also need to do process qual and product qual CP test for the development of Memory is also an enterprise is very important role, that is, through the MRA can be calculated chip level Repair address, through Laser Repair will be CP test in the Repairable die repair work back. Repairable die repair work back through Laser Repair, so as to ensure that the field and reliability of the two sides face to face capacity enhancement.

CP is the process of testing wafers to check the production level of the wafer fab, and FT is the testing of packaging to check the production process level of the packaging fab. For the test items, some test items in CP will be tested and do not need to be tested again in FT, saving the time of FT test; however, some tests must be carried out in FT (different design companies have different requirements). Generally speaking, the more CP test items, the more complete; FT test items are fewer, but they are all key items with strict conditions. However, there are many companies that only do FT without CP (if both FT and package rate are high, CP is meaningless). In terms of testing, CP is more difficult to make probe cards, wafer level testingand there is more interference with parallel testing.

FT is simpler. One more thing, CP for memory testing can be difficult because it is cumbersome to write programs to do redundancy analysis.

CP is considered a semi-finished test throughout the production process. It has two purposes. The first is to monitor the yield of the front-end process. The second is to reduce the cost of the back-end process (to avoid packing too many bad chips). In the simplest example, when it comes to high current test items, the CP must be ductile (the probe only allows a limited amount of current), which can only be measured in the FT. However, when FT (for efficiency), many of the tests after CP can be avoided, so it sometimes feels like there are far fewer test items than CP. It should be said that the Wat test program is different from the CP/FT test program.

CP is not measured in terms of fabrication (FAB), CP entries are subordinate to FT (i.e. CP will only measure less than FT), and the entries are exactly the same; the difference is only in the card specification; since packaging can cause parameter drift, CP test specification is more stringent than ft to ensure the final product FT yield. There are quite a few DHs that make wafers into several series of generic cores, and in CP it's determined by trimming the edges to make it into one of their series, which is the best solution to save photolithography plates for similar circuits. So unless your company's wafers are packaged into unique devices with WAT yields around 99%, it's a blind seal.

Currently there is very little research on blind sealed DH's very little, risk management is really not too big to be controlled.

CP uses PROBER, probe card, FT is the manager, socket. Common CP is room temperature = 25 degrees, FT is usually 75 or 90 degrees. CP has no QA buyout (quality certification, acceptance), FT has CP in two ways

1. monitor the process, so I think probe actually belongs to the FAB category.

2. control costs. Economic fate. We know that FT packaging and test costs make up a large portion of the cost of the chip, so it is best to control costs by rejecting or repairing chips with defects in the probes

FT:Final test is usually the test with the most test items, and some customers also require 3-temperature test, which is also the most expensive. As for test items.

1. if the test work time is very long, CP and FT can be measured, like trim items, add in probe can significantly reduce the cost of learning time management, of course, we also need to look at customer service requirements.

2. Regarding high current testing, FT is more, but I have also measured power MOSFETs with probes over 10 amps and more than 10 pins on a PAD.

3. some pads will be encapsulated into the device and can't be seen in FT, so some test items can only be measured directly in CP, such as Igss for gate leakage current test of power tubes. the CP test is mainly to pick out the bad molds, fix the molds, and then make sure that the molds are within the basic specs and functioning well. the FT test is mainly to make sure that the chips work within the tight specs when the package is finished. The difficulty of CP is how to pick out the bad mold and fix it in the shortest time. the difficulty of FT is how to make sure that the factory unit can complete all functions in the shortest time.